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1. general description the 74lvc1t45; 74lvch1t45 are single bi t, dual supply transceivers with 3-state outputs that enables bidirectional level transl ation. they feature two 1-bit input-output ports (a and b), a direction control input (dir) and dual supply pins (v cc(a) and v cc(b) ). both v cc(a) and v cc(b) can be supplied at any voltage between 1.2 v and 5.5 v making the device suitable for translating between an y of the low voltage nodes (1.2 v, 1.5 v, 1.8 v, 2.5 v, 3.3 v and 5.0 v). pins a and dir are referenced to v cc(a) and pin b is referenced to v cc(b) . a high on dir allows transmission from a to b and a low on dir allows transmissi on from b to a. the devices are fully specified for part ial power-down app lications using i off . the i off circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. in suspend mode when either v cc(a) or v cc(b) are at gnd level, both a port and b port ar e in the high-impedance off-state. active bus hold circuitry in the 74lvch1t45 ho lds unused or floating data inputs at a valid logic level. 2. features and benefits ? wide supply voltage range: ? v cc(a) : 1.2 v to 5.5 v ? v cc(b) : 1.2 v to 5.5 v ? high noise immunity ? complies with jedec standards: ? jesd8-7 (1.2 v to 1.95 v) ? jesd8-5 (1.8 v to 2.7 v) ? jesd8c (2.7 v to 3.6 v) ? jesd36 (4.5 v to 5.5 v) ? esd protection: ? hbm jesd22-a114f class 3a exceeds 4000 v ? cdm jesd22-c101e exceeds 1000 v ? maximum data rates: ? 420 mbps (3.3 v to 5.0 v translation) ? 210 mbps (translate to 3.3 v)) ? 140 mbps (translate to 2.5 v) ? 75 mbps (translate to 1.8 v) ? 60 mbps (translate to 1.5 v) ? suspend mode 74lvc1t45; 74lvch1t45 dual supply translati ng transceiver; 3-state rev. 4 ? 27 september 2011 product data sheet
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 2 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state ? latch-up performance exceeds 100 ma per jesd 78 class ii ? ? 24 ma output drive (v cc =3.0v) ? inputs accept voltages up to 5.5 v ? low power consumption: 16 ? a maximum i cc ? i off circuitry provides partial power-down mode operation ? multiple package options ? specified from ? 40 ? cto+85 ? c and ? 40 ? cto+125 ? c 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. table 1. ordering information type number package temperature range name description version 74lvc1t45gw ? 40 ? cto+125 ? c sc-88 plastic surface-mounted package; 6 leads sot363 74lvch1t45gw 74lvc1t45gm ? 40 ? cto+125 ? c xson6 plastic extremely thin sm all outline package; no leads; 6 terminals; body 1 ? 1.45 ? 0.5 mm sot886 74lvch1t45gm 74lvc1t45gf ? 40 ? c to +125 ? c xson6 plastic extremely thin sm all outline package; no leads; 6 terminals; body 1 ? 1 ? 0.5 mm sot891 74lvch1t45gf 74lvc1t45gn ? 40 ? c to +125 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 0.9 ? 1.0 ? 0.35 mm sot1115 74lvch1t45gn 74LVC1T45GS ? 40 ? c to +125 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 1.0 ? 1.0 ? 0.35 mm sot1202 74lvch1t45gs table 2. marking type number marking code [1] 74lvc1t45gw v5 74lvch1t45gw x5 74lvc1t45gm v5 74lvch1t45gm x5 74lvc1t45gf v5 74lvch1t45gf x5 74lvc1t45gn v5 74lvch1t45gn x5 74LVC1T45GS v5 74lvch1t45gs x5
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 3 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 5. functional diagram 6. pinning information 6.1 pinning 6.2 pin description fig 1. logic symbol fig 2. logic diagram 001aag885 v cc(b) v cc(a) 5 dir 3 a b 4 001aag886 v cc(b) v cc(a) dir a b fig 3. pin configuration sot363 (sc-88) fig 4. pin configuration sot886 (xson6) fig 5. pin configuration sot891, sot1115 and sot1202 74lvc1t45 74lvch1t45 v cc(a) v cc(b) gnd ab 001aaj991 1 2 3 6 dir 5 4 74lvc1t45 74lvch1t45 gnd 001aaj992 v cc(a) a dir v cc(b) b transparent top view 2 3 1 5 4 6 74lvc1t45 74lvch1t45 gnd 001aaj993 v cc(a) a dir v cc(b) b transparent top view 2 3 1 5 4 6 table 3. pin description symbol pin description v cc(a) 1 supply voltage port a and dir gnd 2 ground (0 v) a 3 data input or output b 4 data input or output dir 5 direction control v cc(b) 6 supply voltage port b
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 4 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 7. functional description [1] h = high voltage level; l = low voltage level; x = don?t care; z = high-impedance off-state. [2] the input circuit of the data i/o is always active. [3] when either v cc(a) or v cc(b) is at gnd level, the device goes into suspend mode. 8. limiting values [1] the minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are obs erved. [2] v cco is the supply voltage associated with the output port. [3] v cco + 0.5 v should not exceed 6.5 v. [4] for sc-88 package: above 87.5 ? c the value of p tot derates linearly with 4.0 mw/k. for xson6 package: above 118 ? c the value of p tot derates linearly with 7.8 mw/k. 9. recommended operating conditions table 4. function table [1] supply voltage input input/output [2] v cc(a) , v cc(b) dir a b 1.2 v to 5.5 v l a = b input 1.2 v to 5.5 v h input b = a gnd [3] xzz table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc(a) supply voltage a ? 0.5 +6.5 v v cc(b) supply voltage b ? 0.5 +6.5 v i ik input clamping current v i <0v ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o <0v ? 50 - ma v o output voltage active mode [1] [2] [3] ? 0.5 v cco +0.5 v suspend or 3-state mode [1] ? 0.5 +6.5 v i o output current v o =0vtov cco [2] - ? 50 ma i cc supply current i cc(a) or i cc(b) -1 0 0m a i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [4] -2 5 0m w table 6. recommended operating conditions symbol parameter conditions min max unit v cc(a) supply voltage a 1.2 5.5 v v cc(b) supply voltage b 1.2 5.5 v v i input voltage 0 5.5 v
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 5 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state [1] v cco is the supply voltage associated with the output port. [2] v cci is the supply voltage associated with the input port. 10. static characteristics [1] v cco is the supply voltage associated with the output port. [2] v cci is the supply voltage associated with the data input port. [3] to guarantee the node switches, an external driver must source/sink at least i bhlo /i bhho when the input is in the range v il to v ih . v o output voltage active mode [1] 0v cco v suspend or 3-state mode 0 5.5 v t amb ambient temperature ? 40 +125 ?c ? t/ ? v input transition rise and fall rate v cci = 1.2 v [2] - 20 ns/v v cci = 1.4 v to 1.95 v - 20 ns/v v cci = 2.3 v to 2.7 v - 20 ns/v v cci = 3 v to 3.6 v - 10 ns/v v cci = 4.5 v to 5.5 v - 5 ns/v table 6. recommended operating conditions ?continued symbol parameter conditions min max unit table 7. typical static characteristics at t amb = 25 ?c at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit v oh high-level output voltage v i = v ih or v il i o = ? 3 ma; v cco =1.2v [1] -1.09-v v ol low-level output voltage v i = v ih or v il i o = 3 ma; v cco =1.2v [1] -0.07-v i i input leakage current dir input; v i = 0 v to 5.5 v; v cci = 1.2 v to 5.5 v [2] -- ? 1 ? a i bhl bus hold low current a or b port; v i =0.42v;v cci =1.2v [2] -19- ? a i bhh bus hold high current a or b port; v i =0.78v;v cci =1.2v [2] - ? 19 - ? a i bhlo bus hold low overdrive current a or b port; v cci = 1.2 v [2] [3] -19- ? a i bhho bus hold high overdrive current a or b port; v cci = 1.2 v [2] [3] - ? 19 - ? a i oz off-state output current a or b port; v o =0 vor v cco ; v cco = 1.2 v to 5.5 v [1] -- ? 1 ? a i off power-off leakage current a port; v i or v o = 0 v to 5.5 v; v cc(a) =0v;v cc(b) = 1.2 v to 5.5 v -- ? 1 ? a b port; v i or v o = 0 v to 5.5 v; v cc(b) =0v;v cc(a) = 1.2 v to 5.5 v -- ? 1 ? a c i input capacitance dir input; v i = 0 v or 3.3 v; v cc(a) =v cc(b) =3.3v -2.2-pf c i/o input/output capacitance a and b port; suspend mode; v o =3.3vor0v; v cc(a) =v cc(b) =3.3v -6.0-pf
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 6 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state table 8. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max v ih high-level input voltage data input [1] v cci = 1.2 v 0.8v cci -0.8v cci -v v cci = 1.4 v to 1.95 v 0.65v cci -0.65v cci -v v cci = 2.3 v to 2.7 v 1.7 - 1.7 - v v cci = 3.0 v to 3.6 v 2.0 - 2.0 - v v cci = 4.5 v to 5.5 v 0.7v cci -0.7v cci -v dir input v cci = 1.2 v 0.8v cc(a) -0.8v cc(a) -v v cci = 1.4 v to 1.95 v 0.65v cc(a) -0.65v cc(a) -v v cci = 2.3 v to 2.7 v 1.7 - 1.7 - v v cci = 3.0 v to 3.6 v 2.0 - 2.0 - v v cci = 4.5 v to 5.5 v 0.7v cc(a) -0.7v cc(a) -v v il low-level input voltage data input [1] v cci = 1.2 v - 0.2v cci -0.2v cci v v cci = 1.4 v to 1.95 v - 0.35v cci -0.35v cci v v cci = 2.3 v to 2.7 v - 0.7 - 0.7 v v cci = 3.0 v to 3.6 v - 0.8 - 0.8 v v cci = 4.5 v to 5.5 v - 0.3v cci -0.3v cci v dir input v cci = 1.2 v - 0.2v cc(a) -0.2v cc(a) v v cci = 1.4 v to 1.95 v - 0.35v cc(a) - 0.35v cc(a) v v cci = 2.3 v to 2.7 v - 0.7 - 0.7 v v cci = 3.0 v to 3.6 v - 0.8 - 0.8 v v cci = 4.5 v to 5.5 v - 0.3v cc(a) -0.3v cc(a) v v oh high-level output voltage v i = v ih i o = ? 100 ? a; v cco = 1.2 v to 4.5 v [2] v cco ? 0.1 - v cco ? 0.1 - v i o = ? 6ma; v cco = 1.4 v 1.0 - 1.0 - v i o = ? 8ma; v cco = 1.65 v 1.2 - 1.2 - v i o = ? 12 ma; v cco = 2.3 v 1.9 - 1.9 - v i o = ? 24 ma; v cco = 3.0 v 2.4 - 2.4 - v i o = ? 32 ma; v cco = 4.5 v 3.8 - 3.8 - v
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 7 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state v ol low-level output voltage v i = v il [2] i o = 100 ? a; v cco = 1.2 v to 4.5 v - 0.1 - 0.1 v i o = 6 ma; v cco = 1.4 v - 0.3 - 0.3 v i o = 8 ma; v cco = 1.65 v - 0.45 - 0.45 v i o = 12 ma; v cco = 2.3 v - 0.3 - 0.3 v i o = 24 ma; v cco = 3.0 v - 0.55 - 0.55 v i o = 32 ma; v cco = 4.5 v - 0.55 - 0.55 v i i input leakage current dir input; v i = 0 v to 5.5 v; v cci = 1.2 v to 5.5 v - ? 2- ? 10 ? a i bhl bus hold low current a or b port [1] v i = 0.49 v; v cci =1.4v 15 - 10 - ? a v i = 0.58 v; v cci =1.65v 25 - 20 - ? a v i = 0.70 v; v cci =2.3v 45 - 45 - ? a v i = 0.80 v; v cci =3.0v 100 - 80 - ? a v i = 1.35 v; v cci =4.5v 100 - 100 - ? a i bhh bus hold high current a or b port [1] v i = 0.91 v; v cci =1.4v ? 15 - ? 10 - ? a v i = 1.07 v; v cci =1.65v ? 25 - ? 20 - ? a v i = 1.60 v; v cci =2.3v ? 45 - ? 45 - ? a v i = 2.00 v; v cci =3.0v ? 100 - ? 80 - ? a v i = 3.15 v; v cci =4.5v ? 100 - ? 100 - ? a i bhlo bus hold low overdrive current a or b port [1] [3] v cci = 1.6 v 125 - 125 - ? a v cci = 1.95 v 200 - 200 - ? a v cci = 2.7 v 300 - 300 - ? a v cci = 3.6 v 500 - 500 - ? a v cci = 5.5 v 900 - 900 - ? a i bhho bus hold high overdrive current a or b port [1] [3] v cci = 1.6 v ? 125 - ? 125 - ? a v cci = 1.95 v ? 200 - ? 200 - ? a v cci = 2.7 v ? 300 - ? 300 - ? a v cci = 3.6 v ? 500 - ? 500 - ? a v cci = 5.5 v ? 900 - ? 900 - ? a i oz off-state output current a or b port; v o =0vorv cco ; v cco = 1.2 v to 5.5 v [2] - ? 2- ? 10 ? a table 8. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 8 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state [1] v cci is the supply voltage associated with the data input port. [2] v cco is the supply voltage associated with the output port. [3] to guarantee the node switches, an external driver must source/sink at least i bhlo /i bhho when the input is in the range v il to v ih . [4] for non bus hold parts only (74lvc1t45). i off power-off leakage current a port; v i or v o =0vto5.5v; v cc(a) =0v; v cc(b) = 1.2 v to 5.5 v - ? 2- ? 10 ? a b port; v i or v o =0vto5.5v; v cc(b) =0v; v cc(a) = 1.2 v to 5.5 v - ? 2- ? 10 ? a i cc supply current a port; v i = 0 v or v cci ; i o = 0 a [1] v cc(a) , v cc(b) = 1.2 v to 5.5 v - 8 - 8 ? a v cc(a) , v cc(b) = 1.65 v to 5.5 v - 3 - 3 ? a v cc(a) = 5.5 v; v cc(b) = 0 v - 2 - 2 ? a v cc(a) = 0 v; v cc(b) = 5.5 v ? 2- ? 2- ? a b port; v i = 0 v or v cci ; i o = 0 a v cc(a) , v cc(b) = 1.2 v to 5.5 v - 8 - 8 ? a v cc(a) , v cc(b) = 1.65 v to 5.5 v - 3 - 3 ? a v cc(b) = 5.5 v; v cc(a) = 0 v - 2 - 2 ? a v cc(b) = 0 v; v cc(a) = 5.5 v ? 2- ? 2- ? a a plus b port (i cc(a) ? i cc(b) ); i o =0a; v i =0 vor v cci v cc(a) , v cc(b) = 1.2 v to 5.5 v - 16 - 16 ? a v cc(a) , v cc(b) = 1.65 v to 5.5 v - 4 - 4 ? a ? i cc additional supply current v cc(a) , v cc(b) = 3.0 v to 5.5 v a port; a port at v cc(a) ? 0.6 v; dir at v cc(a) ; b port = open [4] -50-75 ? a dir input; dir at v cc(a) ? 0.6 v; aportat v cc(a) or gnd; b port = open -50-75 ? a b port; b port at v cc(b) ? 0.6 v; dir at gnd; a port = open [4] -50-75 ? a table 8. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 9 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 11. dynamic characteristics [1] t pzh and t pzl are calculated values using the formula shown in section 14.4 ? enable times ? [1] t pzh and t pzl are calculated values using the formula shown in section 14.4 ? enable times ? table 9. typical dynamic characteristics at v cc(a) = 1.2 v and t amb = 25 ?c voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for waveforms see figure 6 and figure 7 symbol parameter conditions v cc(b) unit 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v 5.0 v t plh low to high propagation delay a to b 10.6 8.1 7.0 5.8 5.3 5.1 ns b to a 10.6 9.5 9.0 8.5 8.3 8.2 ns t phl high to low propagation delay a to b 10.1 7.1 6.0 5.3 5.2 5.4 ns b to a 10.1 8.6 8.1 7.8 7.6 7.6 ns t phz high to off-state propagation delay dirtoa 9.49.49.49.49.49.4ns dir to b 12.0 9.4 9.0 7.8 8.4 7.9 ns t plz low to off-state propagation delay dirtoa 7.17.17.17.17.17.1ns dirtob 9.57.87.76.97.67.0ns t pzh off-state to high propagation delay dir to a [1] 20.1 17.3 16.7 15.4 15.9 15.2 ns dir to b [1] 17.7 15.2 14.1 12.9 12.4 12.2 ns t pzl off-state to low propagation delay dir to a [1] 22.1 18.0 17.1 15.6 16.0 15.5 ns dir to b [1] 19.5 16.5 15.4 14.7 14.6 14.8 ns table 10. typical dynamic characteristics at v cc(b) = 1.2 v and t amb = 25 ?c voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for waveforms see figure 6 and figure 7 symbol parameter conditions v cc(a) unit 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v 5.0 v t plh low to high propagation delay a to b 10.6 9.5 9.0 8.5 8.3 8.2 ns b to a 10.6 8.1 7.0 5.8 5.3 5.1 ns t phl high to low propagation delay a to b 10.1 8.6 8.1 7.8 7.6 7.6 ns b to a 10.1 7.1 6.0 5.3 5.2 5.4 ns t phz high to off-state propagation delay dirtoa 9.46.55.74.14.13.0ns dir to b 12.0 6.1 5.4 4.6 4.3 4.0 ns t plz low to off-state propagation delay dirtoa 7.14.94.53.23.42.5ns dirtob 9.57.36.65.95.75.6ns t pzh off-state to high propagation delay dir to a [1] 20.1 15.4 13.6 11.7 11.0 10.7 ns dir to b [1] 17.7 14.4 13.5 11.7 11.7 10.7 ns t pzl off-state to low propagation delay dir to a [1] 22.1 13.2 11.4 9.9 9.5 9.4 ns dir to b [1] 19.5 15.1 13.8 11.9 11.7 10.6 ns
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 10 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state [1] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of the outputs. [2] f i = 10 mhz; v i =gndtov cc ; t r = t f = 1 ns; c l = 0 pf; r l = ? ? . table 11. typical power dissipation capacitance at v cc(a) = v cc(b) and t amb = 25 ?c [1] [2] voltages are referenced to gnd (ground = 0 v). symbol parameter conditions v cc(a) and v cc(b) unit 1.8 v 2.5 v 3.3 v 5.5 v c pd power dissipation capacitance a port: (direction a to b); b port: (direction b to a) 2334pf a port: (direction b to a); b port: (direction a to b) 15 16 16 18 pf table 12. dynamic characteristics for temperature range ? 40 ? c to +85 ?c voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for wave forms see figure 6 and figure 7 symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max v cc(a) = 1.4 v to 1.6 v t plh low to high propagation delay a to b 2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns b to a 2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns t phl high to low propagation delay a to b 2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns b to a 2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2.3 11.0 ns t phz high to off-state propagation delay dir to a 3.0 18.7 3.0 18.7 3. 0 18.7 3.0 18.7 3.0 18.7 ns dir to b 3.5 24.8 3.5 23.6 3. 0 11.0 3.3 11.3 2.8 10.3 ns t plz low to off-state propagation delay dir to a 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns dir to b 2.8 18.3 3.0 17.2 2.5 9.4 3.0 10.1 2.5 9.4 ns t pzh off-statetohigh propagation delay dir to a [1] - 39.6 - 36.3 - 24.3 - 22.5 - 21.4 ns dir to b [1] - 32.7 - 29.0 - 24.9 - 23.2 - 21.9 ns t pzl off-state to low propagation delay dir to a [1] - 44.1 - 40.9 - 24.2 - 22.6 - 21.3 ns dir to b [1] - 38.0 - 34.0 - 30.5 - 29.6 - 29.5 ns v cc(a) = 1.65 v to 1.95 v t plh low to high propagation delay a to b 2.6 19.1 2.2 17.7 2.2 9.3 1.7 7.2 1.4 6.8 ns b to a 2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns t phl high to low propagation delay a to b 2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 ns b to a 2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns t phz high to off-state propagation delay dir to a 2.9 17.1 2.9 17.1 2. 9 17.1 2.9 17.1 2.9 17.1 ns dir to b 3.2 24.1 3.2 21.9 2. 7 11.5 3.0 10.3 2.5 8.2 ns t plz low to off-state propagation delay dir to a 2.4 10.5 2.4 10.5 2. 4 10.5 2.4 10.5 2.4 10.5 ns dir to b 2.5 17.6 2.6 16.0 2.2 9.2 2.7 8.4 2.4 6.4 ns
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 11 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state t pzh off-statetohigh propagation delay dir to a [1] - 35.2 - 33.7 - 25.2 - 23.9 - 21.8 ns dir to b [1] - 29.6 - 28.2 - 19.8 - 17.7 - 17.3 ns t pzl off-state to low propagation delay dir to a [1] - 39.4 - 36.2 - 24.4 - 22.9 - 20.4 ns dir to b [1] - 34.4 - 31.4 - 25.6 - 24.2 - 24.1 ns v cc(a) = 2.3 v to 2.7 v t plh low to high propagation delay a to b 2.3 17.9 2.3 16.0 1.5 8.5 1.3 6.2 1.1 4.8 ns b to a 2.0 13.5 2.2 9.3 1.5 8.5 1.4 8.0 1.0 7.5 ns t phl high to low propagation delay a to b 2.3 15.8 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 ns b to a 1.8 11.8 1.9 8.5 1.4 7.5 1.3 7.0 0.9 6.2 ns t phz high to off-state propagation delay dir to a 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 2.1 8.1 ns dir to b 3.0 22.5 3.0 21.4 2. 5 11.0 2.8 9.3 2.3 6.9 ns t plz low to off-state propagation delay dir to a 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 1.7 5.8 ns dir to b 2.3 14.6 2.5 13.2 2.0 9.0 2.5 8.4 1.8 5.3 ns t pzh off-statetohigh propagation delay dir to a [1] - 28.1 - 22.5 - 17.5 - 16.4 - 12.8 ns dir to b [1] - 23.7 - 21.8 - 14.3 - 12.0 - 10.6 ns t pzl off-state to low propagation delay dir to a [1] - 34.3 - 29.9 - 18.5 - 16.3 - 13.1 ns dir to b [1] - 23.9 - 21.0 - 15.6 - 13.5 - 12.7 ns v cc(a) = 3.0v to 3.6v t plh low to high propagation delay a to b 2.3 17.1 2.1 15.5 1.4 8.0 0.8 5.6 0.7 4.4 ns b to a 1.7 11.8 1.7 7.2 1.3 6.2 0.7 5.6 0.6 5.4 ns t phl high to low propagation delay a to b 2.2 15.6 2.0 12.6 1.3 7.0 0.8 5.0 0.7 4.0 ns b to a 1.7 10.9 1.8 7.1 1.3 5.4 0.8 5.0 0.7 4.5 ns t phz high to off-state propagation delay dir to a 2.3 7.3 2.3 7.3 2.3 7.3 2.3 7.3 2.7 7.3 ns dir to b 2.9 18.0 2.9 16.5 2.3 10.1 2.7 8.6 2.2 6.3 ns t plz low to off-state propagation delay dir to a 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 2.0 5.6 ns dir to b 2.3 13.6 2.4 12.5 1.9 7.8 2.3 7.1 1.7 4.9 ns t pzh off-statetohigh propagation delay dir to a [1] - 25.4 - 19.7 - 14.0 - 12.7 - 10.3 ns dir to b [1] - 22.7 - 21.1 - 13.6 - 11.2 - 10.0 ns t pzl off-state to low propagation delay dir to a [1] - 28.9 - 23.6 - 15.5 - 13.6 - 10.8 ns dir to b [1] - 22.9 - 19.9 - 14.3 - 12.3 - 11.3 ns v cc(a) = 4.5v to 5.5v t plh low to high propagation delay a to b 2.2 16.6 1.9 15.1 1.0 7.5 0.7 5.4 0.5 3.9 ns b to a 1.6 10.5 1.4 6.8 1.0 4.8 0.7 4.4 0.5 3.9 ns t phl high to low propagation delay a to b 2.3 15.3 1.8 12.2 1.0 6.2 0.7 4.5 0.5 3.5 ns b to a 1.7 10.8 1.7 7.0 0.9 4.6 0.7 4.0 0.5 3.5 ns t phz high to off-state propagation delay dir to a 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 1.7 5.4 ns dir to b 2.9 17.3 2.9 16.1 2.3 9.7 2.7 8.0 2.5 5.7 ns table 12. dynamic characteristics for temperature range ? 40 ? c to +85 ?c ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for wave forms see figure 6 and figure 7 symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 12 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state [1] t pzh and t pzl are calculated values using the formula shown in section 14.4 ? enable times ? t plz low to off-state propagation delay dir to a 1.4 3.7 1.4 3.7 1.3 3.7 1.0 3.7 0.9 3.7 ns dir to b 2.3 13.1 2.4 12.1 1.9 7.4 2.3 7.0 1.8 4.5 ns t pzh off-statetohigh propagation delay dir to a [1] - 23.6 - 18.9 - 12.2 - 11.4 - 8.4 ns dir to b [1] - 20.3 - 18.8 - 11.2 - 9.1 - 7.6 ns t pzl off-state to low propagation delay dir to a [1] - 28.1 - 23.1 - 14.3 - 12.0 - 9.2 ns dir to b [1] - 20.7 - 17.6 - 11.6 - 9.9 - 8.9 ns table 12. dynamic characteristics for temperature range ? 40 ? c to +85 ?c ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for wave forms see figure 6 and figure 7 symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max table 13. dynamic characteristics for temperature range ? 40 ? c to +125 ?c voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for wave forms see figure 6 and figure 7 symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max v cc(a) = 1.4 v to 1.6 v t plh low to high propagation delay a to b 2.5 23.5 2.1 19.4 1.8 14.9 1.5 13.0 1.4 11.6 ns b to a 2.5 23.5 2.3 21.1 2.0 16.4 2.0 13.7 1.9 13.2 ns t phl high to low propagation delay a to b 2.3 21.3 1.9 16.9 1.6 13.0 1.5 12.0 1.5 11.9 ns b to a 2.3 21.3 2.1 19.1 2.0 14.6 1.9 12.5 2.0 12.1 ns t phz high to off-state propagation delay dir to a 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 ns dir to b 3.1 27.3 3.1 26.0 2.7 12.1 2.9 12.5 2.5 11.4 ns t plz low to off-state propagation delay dir to a 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 ns dir to b 2.5 20.2 2.7 19.0 2.2 10.4 2.7 11.2 2.2 10.4 ns t pzh off-statetohigh propagation delay dir to a [1] - 43.7 - 40.1 - 26.8 - 24.9 - 23.6 ns dir to b [1] - 36.1 - 32.0 - 27.5 - 25.6 - 24.2 ns t pzl off-state to low propagation delay dir to a [1] - 48.6 - 45.1 - 26.7 - 25.0 - 23.5 ns dir to b [1] - 41.9 - 37.5 - 33.6 - 32.6 - 32.5 ns v cc(a) = 1.65 v to 1.95 v t plh low to high propagation delay a to b 2.3 21.1 1.9 19.5 1.9 10.3 1.5 8.0 1.2 7.5 ns b to a 2.1 19.4 1.9 19.5 2.0 17.6 1.8 17.1 1.7 16.7 ns t phl high to low propagation delay a to b 2.1 19.1 1.8 15.8 1.4 9.4 1.6 7.9 1.5 7.7 ns b to a 1.9 16.9 1.8 15.8 1.8 14.2 1.8 13.9 1.6 13.5 ns t phz high to off-state propagation delay dir to a 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 ns dir to b 2.8 26.6 2.8 24.1 2.4 12.7 2.7 11.4 2.2 9.1 ns t plz low to off-state propagation delay dir to a 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 ns dir to b 2.2 19.4 2.3 17.6 1.9 10.2 2.4 9.3 2.1 7.4 ns t pzh off-statetohigh propagation delay dir to a [1] - 38.8 - 37.1 - 27.8 - 26.4 - 24.1 ns dir to b [1] - 32.7 - 31.1 - 21.9 - 19.6 - 19.1 ns
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 13 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state t pzl off-state to low propagation delay dir to a [1] - 43.5 - 39.9 - 26.9 - 25.3 - 22.6 ns dir to b [1] - 38.0 - 34.7 - 28.3 - 26.8 - 26.6 ns v cc(a) = 2.3 v to 2.7 v t plh low to high propagation delay a to b 2.0 19.7 2.0 17.6 1.3 9.4 1.1 6.9 0.9 5.3 ns b to a 1.8 14.9 1.9 10.3 1.3 9.4 1.2 8.8 0.9 8.3 ns t phl high to low propagation delay a to b 2.0 17.4 1.8 14.2 1.2 8.3 1.1 6.0 0.8 5.1 ns b to a 1.6 13.0 1.7 9.4 1.2 8.3 1.1 7.7 0.8 6.9 ns t phz high to off-state propagation delay dir to a 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 1.8 9.0 ns dir to b 2.7 24.8 2.7 23.6 2.2 12.1 2.5 10.3 2.0 7.6 ns t plz low to off-state propagation delay dir to a 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 1.5 6.4 ns dir to b 2.0 16.1 2.2 14.6 1.8 9.9 2.2 9.3 1.6 5.9 ns t pzh off-statetohigh propagation delay dir to a [1] - 31.0 - 24.9 - 19.3 - 18.1 - 14.2 ns dir to b [1] - 26.1 - 24.0 - 15.8 - 13.3 - 11.7 ns t pzl off-state to low propagation delay dir to a [1] - 37.8 - 33.0 - 20.4 - 18.0 - 14.5 ns dir to b [1] - 26.4 - 23.2 - 17.3 - 15.0 - 14.1 ns v cc(a) = 3.0v to 3.6v t plh low to high propagation delay a to b 2.0 18.9 1.8 17.1 1.2 8.8 0.7 6.2 0.6 4.9 ns b to a 1.5 13.0 1.5 8.0 1.1 6.9 0.6 6.2 0.5 6.0 ns t phl high to low propagation delay a to b 1.9 17.2 1.8 13.9 1.1 7.7 0.7 5.5 0.6 4.4 ns b to a 1.5 12.0 1.6 7.9 1.1 6.0 0.7 5.5 0.6 5.0 ns t phz high to off-state propagation delay dir to a 2.0 8.1 2.0 8.1 2.0 8.1 2.0 8.1 2.4 8.1 ns dir to b 2.6 19.8 2.6 18.2 2.0 11.2 2.4 9.5 1.9 7.0 ns t plz low to off-state propagation delay dir to a 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 1.8 6.2 ns dir to b 2.0 15.0 2.1 13.8 1.7 8.6 2.0 7.9 1.5 5.4 ns t pzh off-statetohigh propagation delay dir to a [1] - 28.0 - 21.8 - 15.5 - 14.1 - 11.4 ns dir to b [1] - 25.1 - 23.3 - 15.0 - 12.4 - 11.1 ns t pzl off-state to low propagation delay dir to a [1] - 31.8 - 26.1 - 17.2 - 15.0 - 12.0 ns dir to b [1] - 25.3 - 22.0 - 15.8 - 13.6 - 12.5 ns v cc(a) = 4.5v to 5.5v t plh low to high propagation delay a to b 1.9 18.3 1.7 16.7 0.9 8.3 0.6 6.0 0.4 4.3 ns b to a 1.4 11.6 1.2 7.5 0.9 5.3 0.6 4.9 0.4 4.3 ns t phl high to low propagation delay a to b 2.0 16.9 1.6 13.5 0.9 6.9 0.6 5.0 0.4 3.9 ns b to a 1.5 11.9 1.5 7.7 0.8 5.1 0.6 4.4 0.4 3.9 ns t phz high to off-state propagation delay dir to a 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 ns dir to b 2.6 19.1 2.6 17.8 2.0 10.7 2.4 8.8 2.2 6.3 ns t plz low to off-state propagation delay dir to a 1.2 4.1 1.2 4.1 1.1 4.1 0.9 4.1 0.8 4.1 ns dir to b 2.0 14.5 2.1 13.4 1.7 8.2 2.0 7.7 1.6 5.0 ns table 13. dynamic characteristics for temperature range ? 40 ? c to +125 ?c ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for wave forms see figure 6 and figure 7 symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 14 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state [1] t pzh and t pzl are calculated values using the formula shown in section 14.4 ? enable times ? 12. waveforms t pzh off-statetohigh propagation delay dir to a [1] - 26.1 - 20.9 - 13.5 - 12.6 - 9.3 ns dir to b [1] - 22.4 - 20.8 - 12.4 - 10.1 - 8.4 ns t pzl off-state to low propagation delay dir to a [1] - 31.0 - 25.5 - 15.8 - 13.2 - 10.2 ns dir to b [1] - 22.9 - 19.5 - 12.9 - 11.0 - 9.9 ns table 13. dynamic characteristics for temperature range ? 40 ? c to +125 ?c ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 ; for wave forms see figure 6 and figure 7 symbol parameter conditions v cc(b) unit 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v 5.0 v ? 0.5 v min max min max min max min max min max measurement points are given in table 14 . v ol and v oh are typical output voltage levels that occur with the output load. fig 6. the data input (a, b) to output (b, a) propagation delay times 001aae967 a, b input b, a output t plh t phl gnd v i v oh v m v m v ol measurement points are given in table 14 . v ol and v oh are typical output voltage levels that occur with the output load. fig 7. enable and disable times 001aae968 t pzl t pzh t phz t plz gnd gnd v i v cco v ol v oh v m v m v m v x v y outputs disabled outputs enabled outputs enabled output low-to-off off-to-low output high-to-off off-to-high dir input
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 15 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state [1] v cci is the supply voltage associated with the data input port. [2] v cco is the supply voltage associated with the output port. [1] v cci is the supply voltage associated with the data input port. [2] dv/dt ? 1.0 v/ns [3] v cco is the supply voltage associated with the output port. table 14. measurement points supply voltage input [1] output [2] v cc(a) , v cc(b) v m v m v x v y 1.2 v to 1.6 v 0.5v cci 0.5v cco v ol +0.1v v oh ? 0.1 v 1.65 v to 2.7 v 0.5v cci 0.5v cco v ol +0.15v v oh ? 0.15 v 3.0 v to 5.5 v 0.5v cci 0.5v cco v ol +0.3v v oh ? 0.3 v test data is given in table 15 . r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance. v ext = external voltage for measuring switching times. fig 8. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae331 v ext v cc v i v o dut c l r t r l r l g table 15. test data supply voltage input load v ext v cc(a) , v cc(b) v i [1] ? t/ ? v [2] c l r l t plh , t phl t pzh , t phz t pzl , t plz [3] 1.2 v to 5.5 v v cci ? 1.0ns/v 15pf 2k ? open gnd 2v cco
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 16 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 13. typical propagation delay characteristics a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 9. typical propagation delay vs load capacitance; t amb = 25 ?c; v cc(a) =1.2v c l (pf) 035 001aai907 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (2) (3) (4) (5) (6) c l (pf) 035 001aai908 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (2) (3) (4) (5) (6) c l (pf) 035 001aai909 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (3) (4) (5) (6) (2) c l (pf) 035 001aai910 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (3) (4) (2)
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 17 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 10. typical propagation delay vs load capacitance; t amb = 25 ?c; v cc(a) =1.5v c l (pf) 035 001aai911 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (3) (4) (2) c l (pf) 035 001aai912 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (3) (4) (2) c l (pf) 035 001aai913 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (3) (4) (2) c l (pf) 035 001aai914 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (3) (4) (2)
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 18 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 11. typical propagation delay vs load capacitance; t amb = 25 ?c; v cc(a) =1.8v c l (pf) 035 001aai915 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (3) (4) (2) c l (pf) 035 001aai916 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (3) (4) (2) c l (pf) 035 001aai917 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (4) (2) (3) c l (pf) 035 001aai918 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (6) (4) (2) (3)
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 19 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 12. typical propagation delay vs load capacitance; t amb = 25 ?c; v cc(a) =2.5v c l (pf) 035 001aai919 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai920 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai921 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai922 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6)
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 20 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 13. typical propagation delay vs load capacitance; t amb = 25 ?c; v cc(a) =3.3v c l (pf) 035 001aai923 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai924 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai925 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai926 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6)
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 21 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state a. high to low propagation delay (a to b) b. low to high propagation delay (a to b) c. high to low propagation delay (b to a) d. low to high propagation delay (b to a) (1) v cc(b) = 1.2 v. (2) v cc(b) = 1.5 v. (3) v cc(b) = 1.8 v. (4) v cc(b) = 2.5 v. (5) v cc(b) = 3.3 v. (6) v cc(b) = 5.0 v. fig 14. typical propagation delay vs load capacitance; t amb = 25 ?c; v cc(a) =5v c l (pf) 035 001aai927 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai928 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai929 14 t phl (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6) c l (pf) 035 001aai930 14 t plh (ns) 0 2 4 6 8 10 12 5 1015202530 (1) (5) (4) (2) (3) (6)
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 22 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 14. application information 14.1 unidirectional logic l evel-shifting application the circuit given in figure 15 is an example of the 74lvc1t45; 74lvch1t45 being used in an unidirectional logic level-shifting application. fig 15. unidirectional logic level-shifting application table 16. description unidirectional logic level-shifting application pin name function description 1v cc(a) v cc1 supply voltage of system-1 (1.2 v to 5.5 v) 2 gnd gnd device gnd 3 a out output level depends on v cc1 voltage 4 b in input threshold value depends on v cc2 voltage 5 dir dir the gnd (low level) determ ines b port to a port direction 6v cc(b) v cc2 supply voltage of system-2 (1.2 v to 5.5 v) 001aaj994 74lvc1t45 74lvch1t45 v cc1 v cc2 v cc1 1 2 3 v cc(a) gnd system-1 system-2 a 6 5 4 v cc(b) dir b v cc2
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 23 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 14.2 bidirectional logic l evel-shifting application figure 16 shows the 74lvc1t45; 74lvch1t45 being used in a bidirectional logic level-shifting application. since the device d oes not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. ta b l e 1 7 gives a sequence that will illu strate data transmission fr om system-1 to system-2 and then from system-2 to system-1. [1] h = high voltage level; l = low voltage level; z = high-impedance off-state. pull-up or pull-down only needed for 74lvc1t45. fig 16. bidirectional logic level-shifting application table 17. description bidirectional logic level-shifting application [1] state dir ctrl i/o-1 i/o-2 description 1 h output input system-1 data to system-2 2 h z z system-2 is getting ready to send data to system-1. i/o-1 and i/o-2 are disabled. the bus-line state depends on bus hold. 3 l z z dir bit is set low. i/o-1 and i/o-2 still are disabled. the bus-line state depends on bus hold. 4 l input output system-2 data to system-1 001aaj995 74lvc1t45 74lvch1t45 v cc1 v cc1 v cc2 v cc2 1 2 3 v cc(a) gnd system-1 system-2 a 6 5 4 v cc(b) dir b i/o-1 i/o-2 pull-up/down dir ctrl pull-up/down
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 24 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 14.3 power-up considerations the device is designed such that no special power-up sequence is required other than gnd being applied first. 14.4 enable times calculate the enable times for the 74lvc1t45; 74lvch1t45 using the following formulas: ? t pzh (dir to a) = t plz (dir to b) + t plh (b to a) ? t pzl (dir to a) = t phz (dir to b) + t phl (b to a) ? t pzh (dir to b) = t plz (dir to a) + t plh (a to b) ? t pzl (dir to b) = t phz (dir to a) + t phl (a to b) in a bidirectional application, these enable times provide the maximum delay from the time the dir bit is switched until an output is expected. for example, if the 74lvc1t45; 74lvch1t45 initially is transmitti ng from a to b, then the dir bit is switched, the b port of the device must be disabled before presenting it with an input. after the b port has been disabled, an input signal applied to it app ears on the corresponding a port after the specified propagation delay. table 18. typical total supply current (i cc(a) + i cc(b) ) v cc(a) v cc(b) unit 0 v 1.8 v 2.5 v 3.3 v 5.0 v 0 v0 < 1< 1< 1< 1 ? a 1.8 v < 1 < 2 < 2 < 2 2 ? a 2.5 v < 1 < 2 < 2 < 2 < 2 ? a 3.3 v < 1 < 2 < 2 < 2 < 2 ? a 5.0 v < 1 2 < 2 < 2 < 2 ? a
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 25 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 15. package outline fig 17. package outline sot363 (sc-88) references outline version european projection issue date iec jedec jeita sot363 sc-88 wb m b p d e 1 e pin 1 index a a 1 l p q detail x h e e v m a a b y 0 1 2 mm scale c x 13 2 45 6 plastic surface-mounted package; 6 leads sot363 unit a 1 max b p cd e e 1 h e l p qy wv mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.1 0.2 dimensions (mm are the original dimensions) 0.45 0.15 0.25 0.15 a 1.1 0.8 04-11-08 06-03-16
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 26 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state fig 18. package outline sot886 (xson6) terminal 1 index area references outline version european projection issue date iec jedec jeita sot886 mo-252 sot886 04-07-15 04-07-22 dimensions (mm are the original dimensions) xson6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 0 1 2 mm scale notes 1. including plating thickness. 2. can be visible in some manufacturing processes. unit mm 0.25 0.17 1.5 1.4 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.50.6 a (1) max 0.5 0.04 1 6 2 5 3 4 6 (2) 4 (2) a
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 27 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state fig 19. package outline sot891 (xson6) terminal 1 index area references outline version european projection issue date iec jedec jeita sot891 sot891 05-04-06 07-05-15 xson6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm d e e 1 e a 1 b l l 1 e 1 0 1 2 mm scale dimensions (mm are the original dimensions) unit mm 0.20 0.12 1.05 0.95 0.35 0.27 a 1 max b e 1.05 0.95 d ee 1 l 0.40 0.32 l 1 0.35 0.55 a max 0.5 0.04 1 6 2 5 3 4 a 6 (1) 4 (1) note 1. can be visible in some manufacturing processes.
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 28 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state fig 20. package outline sot1115 (xson6) references outline version european projection issue date iec jedec jeita sot1115 sot1115_po 10-04-02 10-04-07 unit mm max nom min 0.35 0.04 0.95 0.90 0.85 1.05 1.00 0.95 0.55 0.3 0.40 0.35 0.32 a (1) dimensions note 1. including plating thickness. 2. visible depending upon used manufacturing technology. xson6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm sot1115 a 1 b 0.20 0.15 0.12 deee 1 l 0.35 0.30 0.27 l 1 0 0.5 1 mm scale terminal 1 index area d e (4) (2) e 1 e 1 e l l 1 b 321 6 5 4 (6) (2) a 1 a
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 29 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state fig 21. package outline sot1202 (xson6) references outline version european projection issue date iec jedec jeita sot1202 sot1202_po 10-04-02 10-04-06 unit mm max nom min 0.35 0.04 1.05 1.00 0.95 1.05 1.00 0.95 0.55 0.35 0.40 0.35 0.32 a (1) dimensions note 1. including plating thickness. 2. visible depending upon used manufacturing technology. xson6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm sot1202 a 1 b 0.20 0.15 0.12 deee 1 l 0.35 0.30 0.27 l 1 0 0.5 1 mm scale terminal 1 index area d e (4) (2) e 1 e 1 e l b 123 l 1 6 5 4 (6) (2) a a 1
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 30 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 16. abbreviations 17. revision history table 19. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge hbm human body model table 20. revision history document id release date data sheet status change notice supersedes 74lvc_lvch1t45 v.4 20110927 product data sheet - 74lvc_lvch1t45 v.3 modifications: ? general description corrected (errata). 74lvc_lvch1t45 v.3 20100819 product data sheet - 74lvc_lvch1t45 v.2 modifications: ? added type number 74lvc1t45gn (sot1115/xson6 package). ? added type number 74lvch1t45gn (sot1115/xson6 package). ? added type number 74LVC1T45GS (sot1202/xson6 package). ? added type number 74lvch1t45gs (sot1202/xson6 package). 74lvc_lvch1t45 v.2 20100119 product data sheet - 74lvc_lvch1t45 v.1 74lvc_lvch1t45 v.1 20090511 product data sheet - -
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 31 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lvc_lvch1t45 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 4 ? 27 september 2011 32 of 33 nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvc1t45; 74lvch1t45 dual supply translating transceiver; 3-state ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 27 september 2011 document identifier: 74lvc_lvch1t45 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 recommended operating conditions. . . . . . . . 4 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13 typical propagation delay characteristics . . 16 14 application information. . . . . . . . . . . . . . . . . . 22 14.1 unidirectional logic level-shifting application . 22 14.2 bidirectional logic level-shifting application. . . 23 14.3 power-up considerations . . . . . . . . . . . . . . . . 24 14.4 enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 24 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 30 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 31 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 31 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 19 contact information. . . . . . . . . . . . . . . . . . . . . 32 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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